Configuring the Memory Controller - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

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1.0 English

The axi_noc IP core can be configured to include one or more integrated DDR memory controllers (MCs). In the current release of the tools, a given axi_noc instance can be configured to include 0, 1, 2, or 4 MCs. The MC group appears as a single interleaved memory to all masters connected through the NoC.

In interleave mode, the application sees a single unified block of memory that spans the participating MCs. The NoC supports interleaving across two or four MCs by automatically chopping AXI requests into interleave block sized sub-requests and alternately sending the sub-requests to each of the participating MCs in turn.

If an axi_noc instance is configured for one or more MCs, several additional tabs appear on the customize IP dialog box:

DDR Basic
Allows the configuration of the controller/PHY mode and the clocking options. The controller type can be set to either DDR4 or LPDDR4. The clocking options include setting the memory frequency, and the system clock period and mode.
DDR Memory Options
Allows configuration of memory device options, the memory density parameters, the JEDEC timing parameters of the external DDR and the mode register settings.
DDR Address Mapping Options
Allows the remapping of system address bits to DDR address bits. Three predefined mapping choices are available:
In addition to the predefined choices, you can construct a custom mapping of address bits to row, bank, and column bits.
DDR Advanced
Selects the system address regions and options for ECC, refresh, and power saving modes.