Connectivity Tab - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
Release Date
1.0 English

The Connectivity tab of the IP is shown in the following figure.

Figure 1. Connectivity Tab

The Connectivity tab is used to define the connectivity through the AXI NoC in the form of a matrix as shown in the previous figure. See Connectivity Tab for further details. The rows of the matrix correspond to the AXI PL interfaces and the columns correspond to the HBM pseudo channels of each HBM controller. Each HBM channel has two pseudo channels each with two ports, giving four ports per channel. The previous figure is a result of selecting four HBM channels and four HBM AXI PL slave interfaces per HBM channel. Thus, a total of 16 slave interfaces and eight pseudo channels across four HBM controllers. Port 0 and Port 1 correspond to the even and odd NSU ports on PC0 of an HBM controller and Port 2 and Port 3 correspond to the even and odd NSU ports on PC1.