Core Architecture - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
Release Date
1.0 English

The HBM controller interfaces to user logic in programmable logic (PL) via the programmable Network on Chip (NoC). A pair of NoC slave ports are dedicated to each pseudo channel. An 8x8 switch is added to each quad of HBM pseudo channels. The NoC combined with the switches allow global addressing to the entire HBM stack from any master connected to the NoC.

The following figure shows the HBM controller and the NoC interconnect switches associated with an HBM stack.

Figure 1. Single-Stack HBM2E and NoC Interconnect

The HBM Controller (HBMC) provides user logic access to each HBM stack from the Horizontal NoC (HNoC) and Vertical NoC (VNoC) interconnect paths. The top HNoC has four NoC lanes while the bottom HNoC has two NoC lanes as shown in the following figure for two-stack HBM in a multi super logic region (SLR) device. The VNoC also has two NoC lanes per vertical column. Each NoC lane is bidirectional with independent transmit and receive interfaces.

Figure 2. Dual-Stack HBM2E in a Multi-SLR Device

The top HNoC has 32 HBM_NMUs per stack to saturate the HBM. See HBM_NMU for more details. The following figure shows the top SLR NoC interconnect structure.

Figure 3. Dual-Stack HBM2E and NoC Interconnect in Top SLR Device

The HBM controller consists of a pair of NoC Agent (NA) units, each assigned to one of the two HBM pseudo channels, as shown in the following figure. There are two NSUs (HBM_NSUs) for each pseudo channel. Each pseudo channel has an even NSU (port 0, port 2) and an odd NSU (port1, port 3) connection. Four NSUs provide access to a NoC Agent which performs the following:

  • Checks and generates ECC for the NoC flits.
  • Splits NoC transactions into 32 Byte commands.
  • Arbitrates the transactions to the HBM Controller.
  • Keeps track of transactions that are pending, in process, or completed pending data de-queue.
Important: The HBM controller supports only INCR and WRAP type AXI burst transactions
Figure 4. HBM Controller

The HBM Controller receives the transactions and analyzes them for any coherency requirements then re-orders them to group transactions to minimize excessive page open/closures and read/write turnarounds. These commands are then sent to the PHY to handle the low level transactions with the HBM2E memory channel.