DDR Advanced Tab - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
The DDR Advanced tab is shown in the following figure for reference.
Figure 1. DDR Advanced

Use the DDR Advanced tab to select the required advanced options listed.

2T Timing (DDR4 Only)
Enabled by default for DDR component configurations. For other DDR configurations such as RDIMM/LRDIMM/UDIMM/SODIMM you can either enable or disable this option.
ECC Options
These options are only applicable for ECC enabled designs.
  • Enable Background Scrubbing (DDR4 only): Refer to the ECC Scrubbing section for details. When ECC is enabled for LPDDR4, Background Scrubbing is automatically enabled.
  • Initialize Memory for ECC: This option is enabled by default.
  • ECC Initialization Size (MB): Initialization size can be changed by the user from the default value.
    Note: You are responsible for initializing memory if memory initialization is disabled.
Refresh Options
  • Enable Refresh and Periodic Calibration Interface: Refer to the Refresh section.
  • Fixed fine Granularity Refresh (DDR4 Only): 1x, 2x, 4x. Fixed Fine Granularity Refresh modes can help reduce refresh protocol overhead in high temperature environments. Refer to vendor data sheets for JESD79-4C for more details.
Power Saving Options
Enter the amount of idle clock cycles before controller places the memory in Power Down mode.
Migration Options
Select this to allow adjustment of CAC pin delays. This is necessary for migration from one device to another in the same package. Enabling this option creates an additional tab; Migration Options.