DDR4 single-rank component interfaces with more than nine CK loads will require two CK pairs to be routed on the PCB. Two CK pairs are required to mitigate signal integrity issues resulting from ten or more loads. The integrated memory controller IP outputs two CK pin pairs for single-rank component interfaces resulting in ten or more CK loads. Refer to the Versal Adaptive SoC PCB Design User Guide (UG863) for details on PCB design guidelines.
A 72-bit single-rank, x16 twin die (or dual die) component interface will have ten CK loads. Each x16 twin die (or dual-die) component has two x8 die resulting in two CK loads. The following figure shows the routing guideline for the two CK pairs.
DDR4 dual-rank component interfaces with more than ten CK loads will require two CK pairs to be routed on the PCB. Two CK pairs are required to mitigate signal integrity issues resulting from more than ten loads. The integrated memory controller IP outputs two CK pin pairs for dual-rank component interfaces resulting in ten or more CK loads. Refer to the Versal Adaptive SoC PCB Design User Guide (UG863) for details on PCB design guidelines.
A 72-bit dual-rank, x8 twin die (or dual-die) component interface will have eighteen CK loads. Each x8 twin die (or dual-die) component has two x8 die resulting in two CK loads. The following figure shows the routing guideline for the two CK pairs.
