DDR4 LRDIMM Memory Initialization and Calibration Sequence - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Most of the LRDIMM calibration sequence details are in line with the DDR4 core calibration sequence details as described in the previous Memory Initialization and Calibration Sequence section, unless otherwise stated below.

The following figure shows the overall flow of memory initialization and the different stages of the LRDIMM calibration sequence.

Figure 1. LRDIMM Calibration Sequence
The following data buffer calibration stages are added to meet the timing between the data buffer and DRAMs and these are repeated for every rank of the LRDIMM card/slot.
  • MREP Training
  • MRD Cycle Training
  • MRD Center Training
  • DWL Training
  • MWD Cycle Training
  • MWD Center Training

The host side calibration stages exercise the timing between host and data buffer, and they are performed once for every LRDIMM card/slot.

All the calibration stages between data buffer and DRAMs are exercised first, and then the host side calibration stages are exercised.

At the end of each of the data buffer calibration stages, Per Buffer Addressing (PBA) mode is enabled to program the calibrated latency and delay values into the data buffer registers.

The following sections describe the data buffer calibration stages.