DDR4 Pin Rules - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Note: You are encouraged to try the Obtaining and Verifying Versal ACAP Memory Pinouts tutorial available on GitHub. This is a fast and effective way to quickly generate pinouts for Versal DDRMCs. All pins swaps must be captured in the design's XDC and validated before generating hardware. PCB level pin swaps not captured in the tools may lead to hardware failures if pin rules are not followed.
  1. All Command, Address, Control, and Clock pins are fixed.
    1. Command/Address/Control pins: ACT_N, RAS_N(A[16]), CAS_N(A[15]), WE_N(A[14]), A, BA, BG, CKE, CS_N, ODT, PAR.
    2. Clock pins: CK_T, CK_C.
  2. All DQ/DM/DQS pins are fixed with the following swapping allowed:
    1. DDR4 DQ bit swap.
      1. DQ bits within a nibble can be swapped for x4 based interfaces.
        Table 1. Example of DQ bits swapped within Nibble
        Triplet#Pin# Package pin name Un-swapped x4 Swapped x4 Notes
        MxP0 IO_L0P_XCC_N0P0 DQS0_t   Cannot swap
        MxP1 IO_L0N_XCC_N0P1 DQS0_c   Cannot swap
        MxP2 IO_L1P_N0P2 DQ3 DQ0  
        MxP3 IO_L1N_N0P3 DQ1 DQ2  
        MxP4 IO_L2P_N0P4 DQ2 DQ1  
        MxP5 IO_L2NN0P5 DQ0 DQ3  
      2. DQ bits within a byte can be swapped for x8/x16 based interfaces.
        Table 2. Example of DQ bits swapped within Byte
        Triplet#Pin# Package pin name Un-swapped x8/x16 Swapped x8/x16 Notes
        MxP0 IO_L0P_XCC_N0P0 DM1   Cannot swap
        MxP1 IO_L0N_XCC_N0P1 A12   Cannot swap
        MxP2 IO_L1P_N0P2 DQ11 DQ8  
        MxP3 IO_L1N_N0P3 DQ9 DQ12  
        MxP4 IO_L2P_N0P4 DQ10 DQ14  
        MxP5 IO_L2N_N0P5 DQ8 DQ15  
                 
        MxP6 IO_L3P_XCC_N1P0 DQS1_t   Cannot swap
        MxP7 IO_L3N_XCC_N1P1 DQS1_c   Cannot swap
        MxP8 IO_L4P_N1P2 DQ12 DQ9  
        MxP9 IO_L4N_N1P3 DQ14 DQ13  
        MxP10 IO_L5P_N1P4 DQ13 DQ10  
        MxP11 IO_L5N_N1P5 DQ15 DQ11  
    2. DDR4 DQ nibble/byte swap.
      1. Any byte including the ECC byte (CB) can be swapped with any other byte for x8/x16 based component and DIMM interfaces. DQ bits within the swapped bytes can also be swapped.
        Table 3. Example of Byte1 swapped with Byte0
        Triplet#Pin# Package pin name Un-swapped x8 Swapped x8 Notes
        MxP0 IO_L0P_XCC_N0P0 DM1 DM0 Data Mask only
        MxP1 IO_L0N_XCC_N0P1 A12   Cannot swap
        MxP2 IO_L1P_N0P2 DQ11 DQ3  
        MxP3 IO_L1N_N0P3 DQ9 DQ1  
        MxP4 IO_L2P_N0P4 DQ10 DQ2  
        MxP5 IO_L2N_N0P5 DQ8 DQ0  
                 
        MxP6 IO_L3P_XCC_N1P0 DQS1_t DQS0_t DQSx_t only
        MxP7 IO_L3N_XCC_N1P1 DQS1_c DQS0_c DQSx_c only
        MxP8 IO_L4P_N1P2 DQ12 DQ4  
        MxP9 IO_L4N_N1P3 DQ14 DQ6  
        MxP10 IO_L5P_N1P4 DQ13 DQ7  
        MxP11 IO_L5N_N1P5 DQ15 DQ5  
                 
        MxP12 IO_L6P_GC_XCC_N2P0 DM0 DM1 Data Mask only
        MxP13 IO_L6N_GC_XCC_N2P1 A7   cannot swap
        MxP14 IO_L7P_N2P2 DQ3 DQ11  
        MxP15 IO_L7N_N2P3 DQ1 DQ9  
        MxP16 IO_L8P_N2P4 DQ2 DQ10  
        MxP17 IO_L8N_N2P5 DQ0 DQ8  
                 
        MxP18 IO_L9P_GC_XCC_N3P0 DQS0_t DQS1_t DQSx_t only
        MxP19 IO_L9N_GC_XCC_N3P1 DQS0_c DQS1_c DQSx_c only
        MxP20 IO_L10P_N3P2 DQ4 DQ12  
        MxP21 IO_L10N_N3P3 DQ6 DQ14  
        MxP22 IO_L11P_N3P4 DQ7 DQ13  
        MxP23 IO_L11N_N3P5 DQ5 DQ15  
      2. Any byte including the ECC byte (CB) with any other byte and nibbles within bytes can be swapped for x4 based DIMM interfaces. DQ bits within the swapped nibbles can also be swapped.
        Table 4. Example of swapping Nibbles within a Byte
        Triplet#Pin# Package pin name Un-swapped x4 Swapped x4 Notes
        MxP0 IO_L0P_XCC_N0P0 DQS4_t DQS13_t DQSx_t only
        MxP1 IO_L0N_XCC_N0P1 DQS4_c DQS13_c DQSx_c only
        MxP2 IO_L1P_N0P2 DQ35 DQ37  
        MxP3 IO_L1N_N0P3 DQ34 DQ36  
        MxP4 IO_L2P_N0P4 DQ33 DQ39  
        MxP5 IO_L2N_N0P5 DQ32 DQ38  
                 
        MxP6 IO_L3P_XCC_N1P0 DQS13_t DQS4_t DQSx_t only
        MxP7 IO_L3N_XCC_N1P1 DQS13_c DQS4_c DQSx_c only
        MxP8 IO_L4P_N1P2 DQ37 DQ35  
        MxP9 IO_L4N_N1P3 DQ36 DQ34  
        MxP10 IO_L5P_N1P4 DQ39 DQ33  
        MxP11 IO_L5N_N1P5 DQ38 DQ32  
      3. Any nibble with any other nibble can be swapped for x4 based component interfaces. DQ bits within the swapped nibbles can also be swapped.
        Table 5. Example of swapping any Nibble with any other Nibble
        Triplet#Pin# Package pin name Un-swapped x4 Swapped x4 Notes
        MxP6 IO_L3P_XCC_N1P0 DQS1_t DQS2_t DQSx_t only
        MxP7 IO_L3N_XCC_N1P1 DQS1_c DQS2_c DQSx_c only
        MxP8 IO_L4P_N1P2 DQ4 DQ8  
        MxP9 IO_L4N_N1P3 DQ6 DQ11  
        MxP10 IO_L5P_N1P4 DQ7 DQ10  
        MxP11 IO_L5N_N1P5 DQ5 DQ9  
                 
        MxP54 IO_L0P_XCC_N0P0 DQS2_t DQS1_t DQSx_t only
        MxP55 IO_L0N_XCC_N0P1 DQS2_c DQS1_c DQSx_c only
        MxP56 IO_L1P_N0P2 DQ8 DQ4  
        MxP57 IO_L1N_N0P3 DQ11 DQ6  
        MxP58 IO_L2P_N0P4 DQ10 DQ7  
        MxP59 IO_L2N_N0P5 DQ9 DQ5  
        Important: With DDR4 clamshell interfaces, it is required that CS0 and Byte0 (DQ[7:0]) be associated with the non-mirrored devices in order for calibration to complete successfully.
    3. Swap across memory channels is not allowed. MC channel-0 must not be swapped with MC channel-1.
  3. Reduced DDR4 data width configurations must remove from the highest numbered DQs in order.
    • 72-bit converts to 64-bit by removing DQ71 down to DQ64
  4. In XP I/O bank 700 and bank 800 (not present in all devices), there is an additional bank pin that is used as a reference to calibrate internal on-die termination. The IO_VR_700/IO_VR_800 pin must be externally connected to a 240Ω resistor on the PCB and pulled up to the bank VCCO voltage.
  5. Pinout for RDIMM/LRDIMM is not pin compatible with that of UDIMMs.
  6. Pinout for UDIMM is not pin compatible with that of components.
  7. Pinouts are compatible between x4 and x8 RDIMM/LRDIMM. If PCB compatibility between x4 and x8 RDIMM/LRDIMM is desired, the following pin swapping restrictions apply.
    • DQ bits can only be swapped within a nibble
    • Nibbles cannot be swapped with any other nibble
    • Bytes can be swapped with any other byte
  8. One differential system clock source (sys_clk) is required per integrated DDR MC. Refer to Clocking for details.
  9. If an entire nibble is free then it can be used for non-memory designs.
  10. Multi-component interfaces must use same data width components. For example, a 72-bit interface can use nine x8 components or five x16 components.