DDR4 Pinout for Component Interfaces (Flipped) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Nibble utilization for 72-bit interface using x8, x16, x8 DDP 2 rank, or 3DS components with 1CK pair in the flipped configuration is shown in the following figure. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a reduced data width of 64-bits, nibbles 2 and 3 in addition to nibbles 0, 1, and 8 in the first Bank would be free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 1. Nibble utilization for 72-bit interface using x8, x16, x8 DDP 2 rank, or 3DS components with 1CK (Flipped)

Nibble utilization for 72-bit interface using x8, x16, x8 DDP 2 rank, or 3DS components with 2CK pairs in the flipped configuration is shown in the following figure. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals. For a reduced data width of 64-bits, nibbles 0 and 1 in addition to nibble 8 in the first Bank and nibble 5 in the third Bank would be free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble utilization for 72-bit interface using x8, x16, x8 DDP 2 rank, or 3DS components with 2CK (Flipped)

Nibble utilization for 40-bit interface using x4 DDP (2 Ranks) or 3DS components with 2CK pairs in the flipped configuration is shown in the following figure. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n signals.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 3. Nibble utilization for 40-bit interface using x4 DDP (2 rank) or 3DS components with 2CK (Flipped)