DDR4 Pinout for Single Rank L/RDIMM Interfaces (Flipped) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Nibble utilization for 72-bit, Single Rank L/RDIMM interface with ECC in the flipped configuration is shown in the following figure. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n.
Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 1. Nibble utilization for 72-bit Single rank L/RDIMM with ECC (Flipped)