DDR4 Pinout for UDIMM/SODIMM Interfaces (Flipped) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Nibble utilization for a 72-bit, Single rank UDIMM/SODIMM interface with ECC in the flipped configuration is shown in the following figure. DQ indicates a data nibble, AC indicates an Address/Command/Control nibble, sys_clk indicates a nibble comprising the System Clock pair, RESET_n, and ALERT_n. Note that for a 64-bit, Single rank UDIMM/SODIMM interface without ECC nibbles 2 and 3 in addition to nibbles 0, 1, and 8 in the first Bank would be free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 1. Nibble utilization for 72-bit Single rank UDIMM/SODIMM with ECC (Flipped)

Nibble utilization for a 72-bit, Multi-rank (Single Slot, 2 Rank) UDIMM/SODIMM interface with ECC in the flipped configuration is shown in the following figure. Note that for a 64-bit, Multi-rank (Single Slot, 2 Rank) UDIMM/SODIMM interface without ECC, nibbles 6, and 7 in addition to nibble 8 in the first bank would be free.

Important: The nibble utilization figure is based on the fixed pinout output by Vivado for this configuration.
Figure 2. Nibble utilization for 72-bit Multi-rank (single slot, 2 rank) UDIMM/SODIMM with ECC (Flipped)