DDR4 RDIMM and LRDIMM Interfaces - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The minimum RDIMM/LRDIMM interface configuration is single rank, single slot RDIMM with 72-bits while the maximum is multi-rank multi-slot RDIMM or any LRDIMM with 72-bits. There are two pinout options for buffered DIMMs; either Optimum or Rank Slot and Stack Height Expansion. The minimum and most efficient Optimum pinout option only applies for single rank single slot non-3DS based RDIMMs. If future applications will still only use single rank single slot non-3DS based RDIMMs then the Optimum option can be selected, otherwise for any other application the Slot Rank and Stack Height option must be selected. When any multi-rank, multi-slot or 3DS based RDIMM configuration is selected the only option is Optimum because it already uses the Rank Slot and Stack Height Expansion pinout. When any LRDIMM device is selected the only option is Optimum because it already uses the Rank Slot and Stack Height Expansion pinout. When using any multi-rank multi-slot or 3DS based RDIMM or any LRDIMM device then the existing pinout automatically supports all future RDIMM and LRDIMM topology expansions as well as x4 and x8 device compatibility.

To ensure every future signal is routed correctly the Write DM or any Write/Read DBI function must be enabled to generate the DM/DBI ports. These are critical for x4/x8 compatibility. Also note any requirements for 3DS devices, quad rank, or dual slot topologies and generate the maximum pinout appropriately to ensure the additional DDR4 output clocks and control signals are generated and included in the hardware design. Enable the Command Address parity feature when generating the pinout if it is required.