DDRMC-NSU - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Each DDR memory controller has a partial NSU (DDRMC-NSU) for each port. The DDRMC-NSU serves to convert from the NoC packet domain to the memory controller domain without first converting to AXI protocol.