DM/DBI - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

If the DDRMC configuration has Write DM/DBI or Read DBI functionality disabled, then the IP will not generate these ports in the pinout. In the scenario when future hardware applications need Write Data Mask or Write/Read DBI functionality, then the pinout must be generated with these functions enabled. Write DM and Write/Read DBI functionality is only available for x8 and x16 devices. For RDIMM/LRDIMM devices the JEDEC standard connector handles the mapping for x4 and x8-based devices which includes the DM/DBI pin for x8 components, so no additional care is required in this buffered DIMM scenario. If required for future applications then these functions must be enabled when generating the pinout and ensure these signals are routed to the correct sites on the DDR4 components or DIMM connector.