Calibration Overview
The XPHY is used to capture read data from the NoC by using the DQS strobe to clock in read data and transfer the data to an internal FIFO using that strobe. The first step in capturing data is to evaluate where that strobe is so the XPHY can open the gate and allow the DQS to clock the data into the rest of the PHY.
The XPHY uses an internal clock to sample the DQS during a read burst and provides a single binary value back called GT_STATUS. This sample is used as part of a training algorithm to determine where the first rising edge of the DQS is in relation to the sampling clock.
Calibration logic issues individual read commands to the NoC and asserts the clb2phy_rd_en signal to the XPHY to open the gate which allows the
sample of the DQS to occur. The clb2phy_rd_en signal
has control over the timing of the gate opening on a DRAM-clock-cycle resolution.
This signal is controlled on a per-byte basis in the PHY and is set in the ddr_mc_pi block for use by both calibration and the
controller.
Calibration is responsible for determining the value used on a per-byte basis for use by the controller. The XPHY provides for additional granularity in the time to open the gate through coarse and fine taps. Coarse taps offer 90° DRAM clock-cycle granularity (16 available) and each fine tap provides a 2 to 3 ps granularity for each tap (512 available). BISC provides the number of taps for 1/4 of a memory clock cycle by taking (BRAM_BISC_PQTR_NIBBLE* - BRAM_BISC_ALIGN_PQTR_NIBBLE*) or (BRAM_BISC_NQTR_NIBBLE* - BRAM_BISC_ALIGN_NQTR_NIBBLE*). These are used to estimate the per-tap resolution for a given nibble.
DQS gate calibration algorithm is divided into four parts as shown in flowchart below.
CAL_ERROR Decode for DQS Preamble Detection Calibration
The status of DQS Gate can also be determined by decoding the CAL_ERROR result according to table below.
| Error Code | Description | Recommended Debug Step |
|---|---|---|
| 6 | DQS gating timeout waiting for XPHY gate training done. | Check power and pinout on the PCB/Design. This is the error found when the DRAM does not respond to the Read command. Probe if the read DQS is generated when a read command is sent out. |
| 7 | DQS gating reached maximum read latency limit. | Check DQS and CK trace lengths. Ensure the maximum trace length is not violated. For debug purposes, try a lower frequency where more search range is available and check if the stage is successful. |
| 8 | DQS gating reached maximum read latency limit. | Check DQS and CK trace lengths for all the ranks. Ensure the maximum trace length is not violated. For debug purposes, try a lower frequency. |
| Register Name | Quantity | Description |
|---|---|---|
| Fx_DQSGATE_STG1_OVERFLOW | Rank and Byte | 1 of 16 coarse taps have been used to find the third DQS edge |
| Fx_DQSGATE_STG1_READ_LAT | Rank and Byte | The read latency value after centering on the noise region |
| Fx_DQSGATE_STG1_RLDLYRNK_CRSE | Rank and Byte | The coarse tap value for the third DQS edge |
| Fx_DQSGATE_STG1_RLDLYRNK_FINE | Rank and Byte | The fine tap value for the third DQS edge |
| Fx_DQSGATE_STG2_READ_LAT | Rank and Byte | Read Latency after adjusting for Preamble type (1 or 2TCK) |
| Fx_DQSGATE_STG2_RLDLYRNK_CRSE | Rank and Byte | The coarse tap value after adjusting for Preamble type |
| Fx_DQSGATE_MAX_READ_LAT | 1 | The largest read latency value for all calibrated ranks. For a single rank interface, this value will match DQSGATE_STG2_READ_LAT |
| Fx_DQSGATE_READ_LAT_FINAL | Byte | Final Read Latency value |
| Fx_DQSGATE_RLDLYRNK_CRSE_FINAL | Rank and Byte | Final coarse tap value |