The internal clock strobe is adjusted to align with the DQS returning from the memory. This is performed on all byte lanes in parallel.
This is accomplished as follows:
- Search for the 3rd DQS edge using the initial read latency setting -2 and incrementing coarse taps.
- Search for the noise region using fine taps, and then center on the noise region.
- Adjust the read latency setting (+2) to restore alignment with the first DQS edge as well as account for the detected preamble type (1 or 2 TCK).
- Repeat for each memory rank.
- Adjust the coarse and read latency values to account for the longest delay of all the ranks.
| Register Name | Quantity | Description |
|---|---|---|
| Fx_DQSGATE_STG1_OVERFLOW | Rank and Byte | 1 of 16 coarse taps have been used to find the 3rd DQS edge |
| Fx_DQSGATE_STG1_READ_LAT | Rank and Byte | The read latency value after centering on the noise region |
| Fx_DQSGATE_STG1_RLDLYRNK_CRSE | Rank and Byte | The coarse tap value for the 3rd DQS edge |
| Fx_DQSGATE_STG1_RLDLYRNK_FINE | Rank and Byte | The fine tap value for the 3rd DQS edge |
| Fx_DQSGATE_STG2_READ_LAT | Rank and Byte | Read Latency after adjusting for Preamble type (1 or 2TCK) |
| Fx_DQSGATE_STG2_RLDLYRNK_CRSE | Rank and Byte | The coarse tap value after adjusting for Preamble type |
| Fx_DQSGATE_MAX_READ_LAT | 1 | The largest read latency value for all calibrated ranks. For a single rank interface, this value will match DQSGATE_STG2_READ_LAT |
| Fx_DQSGATE_READ_LAT_FINAL | Byte | Final Read Latency value |
| Fx_DQSGATE_RLDLYRNK_CRSE_FINAL | Rank and Byte | Final coarse tap value |