DQS Gate Tracking - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The DQS sent from the memory is aligned with an internal clock at calibration time, however voltage and temperature may change during operation which will affect the alignment. DQS gate tracking monitors the returning DQS and makes adjustments to the internal clock as necessary to track any variations.

Table 1. DQS Gate Tracking Registers
Register Name Quantity Description
DQSTRACK_RLDLYRNK_CRSE Byte The number of coarse taps for the internal clock
DQSTRACK_RLDLYRNK_FINE Byte The number of fine taps for the internal clock
DQSTRACK_RLDLYRNK_CRSE_MAX Byte The largest number of coarse taps for the internal clock since the tracking started
DQSTRACK_RLDLYRNK_FINE_MAX Byte The largest number of fine taps for the internal clock since the tracking started
DQSTRACK_RLDLYRNK_CRSE_MIN Byte The smallest number of coarse taps for the internal clock since the tracking started
DQSTRACK_RLDLYRNK_FINE_MIN Byte The smallest number of fine taps for the internal clock since the tracking started