DRAM Address Mapping - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

DRAM address mapping is the way the system physical address (for example a 32-bit byte address delivered via AMBA AXI bus) is mapped to the physical DRAM address bits which are partitioned into rows, columns, banks, and bank groups, etc. The address mapping is usually programmable in the DRAM controller and is selected at initialization time. There is no 'one-size-fits-all’ mapping. Different mappings will maximize performance of different workloads or traffic patterns.

Factors affecting choice of mapping include:
  • Address progression: linear, random, rectangular, etc.
  • Transaction size (64, 128, 256 bytes, etc.)
  • Number of threads (that is, the number of individual devices accessing memory)
  • Multi-thread memory space partitioning

It should be noted that it is possible to pick a default address mapping that is a ‘middle-of-the-road’ solution which provides reasonable performance. But for specific use cases that have well-defined traffic patterns and demand for the highest possible performance, the correct choice is crucial.