DRAM Addressing - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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Unlike static RAM (SRAM) in which access to any location is treated equally, DRAM has a specific structure which makes access to different parts incur different overhead. The structure of a typical DRAM includes rows, columns, banks, bank groups, etc.

A DRAM row (or ‘page’) is a block of DRAM space that shares some internal resources and has to be 'opened’ before access to it is possible. A row contains many columns. A typical DRAM may contain 64K rows. Switching between rows incurs a performance penalty due to the required closing of the current row and opening the next row using ‘Precharge’ and ‘Activate’ DRAM commands, and the mandatory minimum allowed time interval between such commands and the next read or write operation.

A DRAM column is a single addressable memory location. A typical DRAM row contains 1024 columns.

A DRAM bank is a group of rows. Within each bank, only a single row can be ‘open’ at any time, and switching between rows is costly. By having multiple banks, multiple rows can be open simultaneously, and switching between rows in different banks can be very efficient. Precharge and Activate commands to different banks can be scheduled concurrently. Typical DDR4 components have 16 banks.

As components got faster and more sophisticated, the concept of bank groups was added (for example in DDR4 and HBM). For example, a DDR4 DRAM has 16 banks arranged in 4 bank groups. A new restriction was added: when switching between banks belonging to different bank groups, there is no performance penalty, but when switching between banks belonging to the same bank group, there is a mandatory wait time of a few clock cycles, leading to lower performance.

Other DRAM partitions such as rank, logical rank (in 3DS), and HBM stack ID (SID) also have some performance implications similar to banks and bank groups.