DRAM Command/Address Parity - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The Command/Address Parity function enables two additional pins in the DDRMC. These are the output only PAR pin and the input only ALERT_N pin. If future hardware designs will be using the Command/Address Parity function, then generate the pinout with this feature enabled. During hardware layout ensure these sites are routed to the correct locations on the DDR4 components or DIMM connectors. When running in application the Command/Address parity feature can be disabled and hardware will operate correctly as these signals are a functional "don’t care".