DRAM-to-DB Read Delay (MRD) Center Training - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

This training aligns Read MDQS in the center of the Read MDQ window at the data buffer. In this training mode, the host pre-programs the data buffer MPR registers with the expected pattern and issues the commands. The data buffer compares the read data with the expected data and feeds back the result on the DQ bus. Calibration finds the left and right edges of the Read MDQ valid window and centers Read MDQS in it.