Data Integrity - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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The Versal adaptive SoC programmable NoC supports end-to-end data protection for AXI memory mapped transactions. In the AXI protocol domain of the NMU and NSU the NoC supports 1 bit per byte of even parity on data lines and 1 bit of even parity on the address. Parity checking in the AXI protocol domain is enabled at configuration time. See Configuring the AXI NoC for more details about how to configure parity checking in the AXI protocol domain. No AXI parity checking is available between the NoC and the PS or AI Engine. Detection of parity errors results in a fatal interrupt.

In the packet domain, after chopping and conversion to the NoC packet format the NoC supports SECDED ECC across the entire flit. The ECC syndrome is completed and checked in the NMU and NSU. No ECC checking is performed in the switch fabric. To detect routing errors an additional parity bit is provided to protect the destination ID field. If a parity error occurs in a switch, the switch signals a fatal error via an interrupt. Packet domain parity and ECC generation and checking is always enabled. For all errors, information is logged about the offending transaction, including the transaction or packet type, the address and the source and destination IDs. Correctable ECC errors are corrected on the fly, and the count of correctable errors is incremented. Uncorrectable ECC errors result in a fatal interrupt.
Note: By default, all interrupts are masked.
Figure 1. End-to-End Protection Overview