Designing with the Core - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The Versal® ACAP tool flow introduces a pair of IP cores, the AXI NoC and the AXI4-Stream NoC (AXIS NoC). These IP cores act as logical representations of the Versal programmable network on chip (NoC). The axi_noc supports the memory mapped AXI protocol while the axis_noc supports the AXI4-Stream protocol. A Versal platform design might include multiple instances of each of these IP cores. Each instance specifies one or more connections to be mapped onto the physical NoC, along with the quality of service requirements for each connection. IP integrator automatically aggregates the connectivity and quality of service information from all of the logical NoC instances to form a unified traffic specification. This traffic specification is used to compute an optimal configuration for the NoC.

The integrated memory controllers (MCs) are integrated into the axi_noc IP core. An instance of the axi_noc can be configured to include one, two, or four instances of the integrated MC. If two or four instances of the MC are selected, they are configured to form a single interleaved memory. If multiple non-interleaved memory controllers are required, each controller requires a separate axi_noc instance.