Dual Channel Component Interfaces - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The minimum Dual Channel DDR4 Component interface configuration is 2 x 16-bit while the maximum is 2 x 32-bit. For all Dual Channel DDR4 Component interface configurations the default pinout is Optimum because fundamentally they all follow the same pinout except for the number of enabled data bytes or the additional Control signals for DDP Deep or 3DS based devices. If future expansion is expected, then generate the pinout based on the maximum 2 x 32-bit interface configuration with the appropriate ECC (if applicable), Command/Address Parity, DM/DBI, and Pinout Swapping options. If using 3DS or DDP Deep devices in the future, then the maximum pinout must have the appropriate options enabled to ensure the additional control signals are generated and routed to the appropriate package pins. JEDEC standards include compatibility for DDP Deep and 3DS based packages with a single hardware design.