ECC - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

Error Correction (Single Error Correct, Double Error Detect) performs checks of read data without interrupting traffic. The ECC calculations are stored in an additional byte, regardless of the data width. For example, a 64-bit DRAM interface with ECC enabled needs an additional byte, making the entire interface 72 bits. Similarly, a 32-bit interface with ECC enabled also needs an additional byte, making the entire interface 40 bits.

For each burst single-bit errors are correctable. Double-bit errors are detectable but uncorrectable. Three or more bit errors may or may not be detected and are not correctable. If any errors are detected, correctable or uncorrectable, they are logged and can be configured to generate an interrupt. Correctable and uncorrectable errors can be injected on write operations.

Note: ECC adds two memory clock cycles of latency during writes when the CAS Write Latency is less than 11.