ECC Error Injection (ECC Poisoning) - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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The DDRMC supports single-bit and dual-bit error injection on system write transaction data. Before starting ECC poisoning, you must stop the regular data traffic. ECC errors can be injected on system write data for selected transactions by configuring associated address mask/match registers and write data bit flip registers to corrupt intended data bits.

Selecting Address to Poison Transaction with ECC Errors under DDRMC_NOC* Registers

Registers reg_adec12 through reg_adec15 configure and enable write transactions for error injection. There is a separate mask and match register field for DRAM address fields. The Mask register masks an address field and the Match register matches an address field. For address bits that are not masked off, the match registers should be programmed with the address value that should match the transaction for error injection.

For example, if none of the address bits are masked off and you want to inject errors only at Row=0x2, Column=0x20, Bank=Group=Rank=LRank=channel=0x0, program the match registers to these values.

Table 1. Error Injection on Write Transactions to a Particular Address
  Row Column Bank Bank_group Rank 3DS Logical Rank DDRMC sub-channel
mask_bit 0x0
match_bit 0x2 0x20 0x0 0x0 0x0 0x0 0x0
match_en 0x1
persistent_bit 0x1
As shown in the previous table, in addition to setting up the mask/match registers, the reg_adec15.match_en and reg_adec15.persistent bits should be set to 0x1 to enable error injection on each write transaction.
Note: If match_en=0x1 and persistent=0x0, only the first transaction will have an error injected.

Selecting Data Bits and Bursts to Poison Transactions with ECC Errors under DDRMC_MAIN* Registers

The eccw0_flip* and eccw1_flip* registers are used to configure which bits of the DDR DQ bus and eccw*_flip_control registers are used to configure which burst within a BLn are corrupted on a transaction that is flagged for error injection by the address mask/match registers.

  • Set eccw0_flip_control to inject error in a burst.
    To insert an error on the first burst set eccw0_flip_control to 0x0000_0001.
  • Set eccw0_flip0 to inject errors on bits [31:0].
    To insert bit errors on bit 31 and 3 of the data set eccw0_flip0 to 0x8000_0008.

The following table shows which eccw*_flip* register affects which DQ bus bits for each DDR bus configuration.

  DDR4 x72 DDR4 x40 DDR4 x24 LP4 x40 LP4 x24
eccw0/1_flip0 DQ[15:0] DQ[15:0] DQ[15:0] DQ[15:0] DQ[15:0]
eccw0/1_flip0 DQ[31:16] DQ[31:16] N/A DQ[31:16] N/A
eccw0/1_flip1 DQ[63:32] N/A N/A N/A N/A
eccw0/1_flip2 DQ[71:64] DQ[39:32] DQ[23:16] DQ[39:32] DQ[23:16]
  1. Errors are never injected on scrub transactions.
  2. The minimum number of bursts with an error injected for LP4 is two.
  3. It is not possible to inject both correctable and uncorrectable errors in a single BLn burst.
  4. eccw0/1 indicates DDRMC channel number, except for DDR4 x72 in which both eccw[1:0]_flip* register sets are used.

The following table shows the error injection burst control for each configuration. As mentioned above, both eccw[1:0]_flip* register sets are used for DDR4 x72, as shown explicitly in the following table. For all other configurations the eccw[n]_flip* register set is used on a per-channel basis, where 'n' is the DDRMC sub-channel number.

Note: For LP4, each flip_control register is used twice, so that the minimum number of bursts with an error injected for LP4 is two.
Note: There is only one set of eccw[1:0]_flip registers for each channel, not a set per burst position. Therefore each burst selected for error injection by a flip_enable register will receive the same error, and it is not possible to inject both correctable and uncorrectable errors in a single BLn burst.
Table 2. Error Injection Burst Control per Configuration
  DDR4 x72 Other DDR4 LP4
Burst0 eccw0_flip_control.flip_enable_00 eccw[1:0]_flip_control.flip_enable_00 eccw[1:0]_flip_control.flip_enable_00
Burst1 eccw0_flip_control.flip_enable_02 eccw[1:0]_flip_control.flip_enable_01 eccw[1:0]_flip_control.flip_enable_01
Burst2 eccw1_flip_control.flip_enable_00 eccw[1:0]_flip_control.flip_enable_02 eccw[1:0]_flip_control.flip_enable_02
Burst3 eccw1_flip_control.flip_enable_02 eccw[1:0]_flip_control.flip_enable_03 eccw[1:0]_flip_control.flip_enable_03
Burst4 eccw0_flip_control.flip_enable_10 eccw[1:0]_flip_control.flip_enable_10 eccw[1:0]_flip_control.flip_enable_10
Burst5 eccw0_flip_control.flip_enable_12 eccw[1:0]_flip_control.flip_enable_11 eccw[1:0]_flip_control.flip_enable_11
Burst6 eccw1_flip_control.flip_enable_10 eccw[1:0]_flip_control.flip_enable_12 eccw[1:0]_flip_control.flip_enable_12
Burst7 eccw1_flip_control.flip_enable_12 eccw[1:0]_flip_control.flip_enable_13 eccw[1:0]_flip_control.flip_enable_13
Burst8     eccw[1:0]_flip_control.flip_enable_00
Burst9     eccw[1:0]_flip_control.flip_enable_01
Burst10     eccw[1:0]_flip_control.flip_enable_02
Burst11     eccw[1:0]_flip_control.flip_enable_03
Burst12     eccw[1:0]_flip_control.flip_enable_10
Burst13     eccw[1:0]_flip_control.flip_enable_11
Burst14     eccw[1:0]_flip_control.flip_enable_12
Burst15     eccw[1:0]_flip_control.flip_enable_13