General Configuration - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Confirm that the IP settings are as expected. Access the settings in the Hardware Manager GUI > Core Properties > Configuration tab.
Table 1. Debug Registers
Register Name Description (in decimal)
MEM_TYPE

1: Integrated Memory Controller DDR4

2: Integrated Memory Controller LPDDR4

3: Soft IP DDR4

PHY_RANKS Number of XPHY Ranks
MEM_RANKS Number of Memory Ranks
BYTES Number of Bytes in the Memory Interface
NIBBLES Number of Nibbles in the Memory Interface
BITS_PER_BYTE Bits per byte (4 or 8)
DBI_PINS Number of DBI pins
SLOTS Number of Slots in the Memory Interface
DIMM_TYPE

0: Component

1: UDIMM

2: RDIMM

3: LRDIMM

LRANKS Number of Logical Ranks
NUM_CHANNELS Number of Memory Channels
DRAM_SIZE Size of the DRAM components
SYS_CLK_8_0 Concatenate the two nine bit registers , SYS_CLK_17_9 and SYS_CLK_8_0 to represent the system clock period in pS
SYS_CLK_17_9 Concatenate the two nine bit registers , SYS_CLK_17_9 and SYS_CLK_8_0 to represent the system clock period in pS
ECC_EN 1 if ECC is enabled
REF_EN 1 if User Controlled Refresh is enabled
PER_RD_EN 1 if Periodic Reads are enabled. 0 if ECC Scrubbing is enabled.
SCRUB_EN 1 if ECC Scrubbing is enabled