- Verify that the system clock frequency on hardware matches the IP setting (Input System Clock Period).
- Verify all guidelines in the Memory Interface chapter of the Versal ACAP PCB Design User Guide (UG863) have been followed.
- Check the rules on the pin and bank options in DDR Memory Controller (see
Pinout Rules).Recommended: You are encouraged to try the Obtaining and Verifying Versal ACAP Memory Pinouts tutorial available on GitHub. This is a fast and effective way to quickly generate pinouts for Versal DDRMCs. All pins swaps must be captured in the design's XDC and validated before generating hardware. PCB level pin swaps not captured in the tools may lead to hardware failures if pin rules are not followed.
- Measure voltages on the board during idle and non-idle times to ensure the
voltages are set appropriately and the noise is within specifications.
Important: LPDDR4/4X protocol uses feedback on the DQ bits during CA Training and Write Leveling calibration stages so any pin swapping needs to be done and validated in the tools. Additionally the DQ mapping from the ACAP to the LPDDR4/4X component channels needs to maintain an exact 1:1 mapping. For example, LPDDR4_DQ_A must be connected to DQ0 of Channel A of the LPDDR4 component. It follows LPDDR4_DQ_A is connected to DQ1 of Channel A, through LPDDR4_DQ_B is connected to DQ15 of Channel B of the LPDDR4 component.
- Ensure the termination voltage regulator (Vtt) is powered to Vcco/2.
- Scope the clock input to verify frequency and signal quality.
- Check the termination registers for the proper values. These are detailed in the Memory Interface chapter of the Versal ACAP PCB Design User Guide (UG863).
- Perform general signal integrity analysis:
- Observe DQ and DQS signals using a scope at the memory. View the alignment of the signals and the Vil/Vih levels during both reads and writes and the overall signal integrity.
- Observe the Address and Command signals on a scope at the memory. View the alignment of the signals and the Vil/Vih levels and the overall signal integrity.
- Verify the memory parts on the board match the settings set in the Memory IP. The timing parameters must match between the IP and the physical part.
- Measure CK/CK_N and DQS/DQS_N and the system clock for duty cycle distortion and general signal integrity.
- Verify timing constraint rules (trace matching) are being met as documented in the Memory Interface chapter of the Versal ACAP PCB Design User Guide (UG863).