Generating Future Expansion Pinouts - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Generating future expansion pinouts for LPDDR4/4X designs is a simpler than for DDR4 based designs. Only the Dual Channel 2 x 32-bit LPDDR4/4X Single Rank Pin Efficient pinout is unique and doesn’t support other LPDDR4/4X configurations. The standard Optimum pinout which is not Pin Efficient will support future expandability for dual rank devices, enabling an ECC device, expanding single channel data widths, expanding dual channel data widths, and expanding from single channel to dual channel topologies. As long as the connection examples are followed multiple topologies can be supported with a single hardware design. While the logical net names change the hardware can remain unchanged. When generating the maximum pinout ensure settings like ECC, Write DM, DBI, and DDRMC Pinout Swapping settings are set as expected for the application. Refer to the connection diagrams for the first configuration and the expanded configuration to visualize the commonalities between them to ensure hardware is designed correctly. An easy way to demonstrate this concept it to look at the Single Channel 16-bit connection diagram, then the Dual Channel 2 x 16-bit connection diagram, then the Single Channel 1 x 32-bit connection diagram, then the Single Channel 1 x 48-bit connection diagram, and then finally a Dual Channel 2 x 32-bit connection diagram.
Figure 1. Connections for a 1x16 LPDDR4/4x Interface
Figure 2. Connections for a 2x16 LPDDR4/4x Interface
Figure 2. Connections for a 1x32 LPDDR4/4x Interface
Figure 3. Connections for a 1x32 with ECC (or 1x48) LPDDR4/4x Interface
Figure 4. Connections for a 2x32 LPDDR4/4x Interface