HBM Configuration Tab - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
Release Date
1.0 English

The AXI_NoC IP core can be configured to include a subset or all of the integrated HBM controllers. Enabling an HBM controller will add the HBM Configuration tab.

Figure 1. HBM Configuration Tab
Configure all Channels to Same Value?
Select Yes to configure all memory controllers to use the same settings. Select No to allow memory controller options to be configured independently.
HBM Clock
Select between internal clock (HSM0) or the external clock pins for the HBM.
HBM Memory Frequency for Stack
Select the operating frequency of the HBM.
HBM Reference Frequency for Stack
Select the frequency provided to the reference clock port. Internal clock has a range of 100-200 MHz and the external clock has a range of 100-500 MHz.
Configure Channels
Click this button to choose the options for the HBM Controllers.
Enable DFI_Clock/2 port
This creates an output clock port that has a frequency equal to the HBM clock/4.