HBM Controller Feature Summary - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English
  • Command reordering for enhanced SDRAM efficiency
  • Maintains ordering for Read/Write after Write coherency
  • ECC Support: Single Error Correct, Dual Error Detect
  • Read and Write Data Parity
  • Command and Address Parity
  • Data Mask and Dynamic Bus Inversion (DBI)
  • Single Bank Refresh Mode
  • All Bank Refresh Optimization
  • Performance Monitoring Registers
  • Memory Protection via AMD Memory Protection Unit (XMPU)
  • Activity-based Power-Down Entry/Exit
  • Activity-based Self-Refresh Entry/Exit
Note: FIXED AXI burst transactions are not supported.