- Command reordering for enhanced SDRAM efficiency
- Maintains ordering for Read/Write after Write coherency
- ECC Support: Single Error Correct, Dual Error Detect
- Read and Write Data Parity
- Command and Address Parity
- Data Mask and Dynamic Bus Inversion (DBI)
- Temperature Controlled Refresh
- Single Bank Refresh Mode
- All Bank Refresh Optimization
- Performance Monitoring Registers
- Memory Protection via Xilinx Memory Protection Unit (XMPU)
- Activity-based Power-Down Entry/Exit
- Activity-based Self-Refresh Entry/Exit