|
Core Specifics |
| Supported Device Family
1
|
Versal®
ACAP |
| Supported User Interfaces |
AXI4 and AXI4-Stream
|
| Provided with
Core
|
| Design Files |
RTL |
| Example Design |
N/A |
| Test Bench |
Verilog |
| Constraints File |
XDC |
| Simulation Model |
SystemVerilog, SystemC |
| Supported S/W Driver |
N/A |
| Tested Design
Flows
2
|
| Design Entry |
Vivado®
IP integrator |
| Simulation |
For supported simulators, see the Xilinx Design Tools: Release Notes
Guide. |
| Synthesis |
Vivado Synthesis |
| Support |
| Release Notes and Known Issues |
Master Answer Record: 75764
|
| All Vivado IP Change
Logs |
Master Vivado IP Change Logs:
72775
|
|
Xilinx
Support web page
|
- For a complete list of supported devices, see
the Vivado IP catalog.
- For the supported versions of third-party
tools, see the Xilinx Design Tools: Release Notes
Guide.
|