IP Facts - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2023-11-01
Version
1.0 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 AMD Versal™ Adaptive SoC
Supported User Interfaces AXI4 and AXI4-Stream
Provided with Core
Design Files RTL
Example Design N/A
Test Bench Verilog
Constraints File XDC
Simulation Model SystemVerilog, SystemC
Supported S/W Driver N/A
Tested Design Flows 2
Design Entry AMD Vivado™ IP integrator
Simulation For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 75764
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete list of supported devices, see the Vivado IP catalog.
  2. For the supported versions of third-party tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).