Internal System Clock - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2023-11-01
Version
1.0 English

To use an internally generated system clock, change System Clock on the DDR Basic tab from Differential to Internal, as shown in the following figure. This adds the sys_clk0 port to the AXI NoC symbol. If this NoC instance includes more than one DDRMC, multiple sys_clk ports will appear, one per DDRMC. These sys_clk ports must be connected to the HSM1 clock output from CIPS. This clock port is not normally shown on the CIPS instance. To make it visible, use the following Tcl command:

set_property -dict [ list CONFIG.PS_PMC_CONFIG { PMC_HSM1_CLk_OUT_ENABLE 1 } ] [ get_bd_cells versal_cips_0 ]
Figure 1. Internal System Clock Selection

The HSM1 output frequency from CIPS must correspond to the Input System Clock Period (ps) selected on the DDR Basic tab. The HSM1 output frequency can be adjusted on the Output Clocks tab of the CIPS configuration screen, as shown in the following figure.

Figure 2. HSM1 Clock Frequency Adjustment