LPDDR4/4X SDRAM provides a mechanism for training the command bus prior to enabling termination for high-frequency operation. For operation above 1866 Mb/s, this stage of training uses the Command Bus Training mode to align the CS and CA signals at the DRAM relative to CK. In this mode, the DRAM uses CS and CK to capture the values on the CA pins, and it feeds the result back to the controller on the DQ[13:8] pins. The training is accomplished in two phases: CS Training and CA Training.
CS Training is completed first to align CS transitions with the falling edge of CK. A static pattern is driven on the CA pins, while the CS to CK timing is varied. By comparing the pattern received on the DQ pins relative to the pattern sent on the CA pins, the controller can identify the noise region. When this has been completed, the CS delay is adjusted to center the rising CK edge ½ clock cycle away from the center of the noise region. After aligning CS to CK, CA Training uses a toggling pattern on the CA lines to deskew and center the CA signals relative to CK.
There are no debug registers for this calibration stage.