LPDDR4/4X Pin Rules - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
Important: LPDDR4/4X protocol uses feedback on the DQ bits during CA Training and Write Leveling calibration stages so any pin swapping needs to be done and validated in the tools. Additionally the DQ mapping from the ACAP to the LPDDR4/4X component channels needs to maintain an exact one-to-one mapping. For example, LPDDR4_DQ_A[0] must be connected to DQ0 of Channel A of the LPDDR4 component, LPDDR4_DQ_A[1] must be connected to DQ1 of Channel A, through LPDDR4_DQ_B[15] that must be connected to DQ15 of Channel B of the LPDDR4 component. You are encouraged to try the Obtaining and Verifying Versal ACAP Memory Pinouts tutorial available on GitHub. This is a fast and effective way to quickly generate pinouts for Versal DDRMCs. All pins swaps must be captured in the design's XDC and validated before generating hardware. PCB level pin swaps not captured in the tools may lead to hardware failures if pin rules are not followed.
  1. All Command, Address, Control, and Clock pins are fixed.
    1. Command/Address/Control pins: CA_A, CA_B, CKE_A, CKE_B, CS_A, CS_B.
    2. Clock pins: CK_T, CK_C.
  2. All DQ/DM/DQS pins are fixed with the following swapping allowed:
    1. LPDDR4/4X DQ bit swap.
      Important: LPDDR4/4X protocol uses feedback on the DQ bits during CA Training and Write Leveling calibration stages so any pin swapping needs to be done and validated in the tools. Additionally the DQ mapping from the ACAP to the LPDDR4/4X component channels needs to maintain an exact 1:1 mapping. For example, LPDDR4_DQ_A[0] must be connected to DQ0 of Channel A of the LPDDR4 component. It follows LPDDR4_DQ_A[1] is connected to DQ1 of Channel A, through LPDDR4_DQ_B[15] is connected to DQ15 of Channel B of the LPDDR4 component.
      1. DQ bits within a byte can be swapped.
        Table 1. Example of DQ Bits swapped within a Byte
        Triplet#Pin# Package pin name Un-swapped Swapped Notes
        MxP0 IO_L0P_XCC_N0P0 DMI3_0   Cannot swap
        MxP1 IO_L0N_XCC_N0P1 CS0_B_0   Cannot swap
        MxP2 IO_L1P_N0P2 DQ30_0 DQ25_0  
        MxP3 IO_L1N_N0P3 DQ31_0 DQ28_0  
        MxP4 IO_L2P_N0P4 DQ27_0 DQ29_0  
        MxP5 IO_L2N_N0P5 DQ26_0 DQ30_0  
        MxP6 IO_L3P_XCC_N1P0 DQS3_T_0   Cannot swap
        MxP7 IO_L3N_XCC_N1P1 DQS3_C_0   Cannot swap
        MxP8 IO_L4P_N1P2 DQ29_0 DQ24_0  
        MxP9 IO_L4N_N1P3 DQ28_0 DQ27_0  
        MxP10 IO_L5P_N1P4 DQ24_0 DQ31_0  
        MxP11 IO_L5N_N1P5 DQ25_0 DQ26_0  
    2. LPDDR4/4X DQ byte swap.
      1. Swap of bytes between x16 halves (within channel A or B of LPDDR4/4X device). As shown in the example, DQ[7:0] and associated DQS0 can be swapped with DQ[15:8] and associated DQS1. However, DQ[15:0] (channel A) must not be swapped with DQ[31:16] (channel B).
        Table 2. Example of Bytes swapped within each channel
        Triplet#Pin# Package pin name Un-swapped Swapped Notes
        MxP78 IO_L12P_GC_XCC_N4P0 DQS0_T_0 DQS1_T_0 DQSx_T only
        MxP79 IO_L12N_GC_XCC_N4P1 DQS0_C_0 DQS1_C_0 DQSx_C only
        MxP80 IO_L13P_N4P2 DQ0_0 DQ13_0  
        MxP81 IO_L13N_N4P3 DQ1_0 DQ12_0  
        MxP82 IO_L14P_N4P4 DQ2_0 DQ9_0  
        MxP83 IO_L14N_N4P5 DQ3_0 DQ14_0  
        MxP84 IO_L15P_XCC_N5P0 DMI0_0 DMI1_0 Data Mask only
        MxP85 IO_L15N_XCC_N5P1 NC    
        MxP86 IO_L16P_N5P2 DQ7_0 DQ8_0  
        MxP87 IO_L16N_N5P3 DQ6_0 DQ15_0  
        MxP88 IO_L17P_N5P4 DQ4_0 DQ10_0  
        MxP89 IO_L17N_N5P5 DQ5_0 DQ11_0  
                 
        MxP12 IO_L6P_GC_XCC_N2P0 DQS1_T_0 DQS0_T_0 DQSx_T only
        MxP13 IO_L6N_GC_XCC_N2P1 DQS1_C_0 DQS0_C_0 DQSx_C only
        MxP14 IO_L7P_N2P2 DQ13_0 DQ0_0  
        MxP15 IO_L7N_N2P3 DQ12_0 DQ1_0  
        MxP16 IO_L8P_N2P4 DQ9_0 DQ2_0  
        MxP17 IO_L8N_N2P5 DQ14_0 DQ3_0  
        MxP18 IO_L9P_GC_XCC_N3P0 DMI1_0 DMI0_0 Data Mask only
        MxP19 IO_L9N_GC_XCC_N3P1 CS1_B_0   Cannot swap
        MxP20 IO_L10P_N3P2 DQ8_0 DQ7_0  
        MxP21 IO_L10N_N3P3 DQ15_0 DQ6_0  
        MxP22 IO_L11P_N3P4 DQ10_0 DQ4_0  
        MxP23 IO_L11N_N3P5 DQ11_0 DQ5_0  
    3. Swap across memory channels is not allowed. MC channel-0 must not be swapped with MC channel-1.
  3. In XP I/O bank 700 and bank 800 (not present in all devices), there is an additional bank pin that is used as a reference to calibrate internal on-die termination. The IO_VR_700/IO_VR_800 pin must be externally connected to a 240Ω resistor on the PCB and pulled up to the bank VCCO voltage..
  4. One differential system clock source (sys_clk) is required per integrated DDR MC. Refer to Clocking for details.
  5. If an entire nibble is free then it can be used for non-memory designs.