LPDDR4/4X Pinout for Supported Configurations - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Supported configurations for LPDDR4/4X are listed under Memory Configuration Support in the DDR Memory Controller section of this Product Guide.

Important: LPDDR4/4X protocol uses feedback on the DQ bits during CA Training and Write Leveling calibration stages so any pin swapping needs to be done and validated in the tools. Additionally the DQ mapping from the ACAP to the LPDDR4/4X component channels needs to maintain an exact 1:1 mapping. For example, LPDDR4_DQ_A[0] must be connected to DQ0 of Channel A of the LPDDR4 component. It follows LPDDR4_DQ_A[1] is connected to DQ1 of Channel A, through LPDDR4_DQ_B[15] is connected to DQ15 of Channel B of the LPDDR4 component.