LRDIMM DWL Training - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

This training aligns the Write MDQS phase with the DRAM clock. In this training mode, the data buffer drives the MDQS pulses, the DRAM samples the clock with MDQS and feeds back the result on MDQ. The data buffer forwards this result from MDQ to DQ. Calibration continues to perform this training to find a 0 to 1 transition on the clock sampled with the Write MDQS at the DRAM.

Table 1. DWL Training Register
Register Name Quantity Description
Fx_DB_DWL_MWD_LAT Rank Data Buffer phase [8:6] and Data Buffer to DRAM latency [5:0]