LRDIMM MREP Training - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
MREP training aligns the Read MDQS phase with the data buffer clock. In this training mode the memory controller sends a sequence of read commands, the DRAM sends out the MDQS, the data buffer samples the strobe with the clock and feeds the result back on DQ. Calibration continues to perform this training to find the 0 to 1 transition on the Read MDQS sampled with the data buffer clock.
Table 1. MREP Training Register
Register Name Quantity Description
Fx_DB_MREP_MRD_LAT Rank MRD latency [8:6] and MREP phase [5:0]