Memory Controller Interleaving - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The NMU supports interleaving memory transactions across two or four hardened memory controllers. The memory regions can be programmed to be interleaved at a granularity of 128 bytes to 4 KBytes, or may be programmed to disable interleaving. The choice of whether to interleave, the interleave granularity, and the address of the interleaved region are determined at the time the NoC is configured. The interleave granularity must match the stripe size of the CCI-500 if the PS full power domain is enabled. The default stripe size for the CCI-500 is 4kB.

When configured to support interleaved memory controllers, the NMU is configured to stripe transactions bound for the DDR across the two or four memory controllers as follows:
  1. The transaction is chopped into smaller packets to align with the memory space of each physical channel. Packet chopping occurs on the interleave boundary between each memory channel.
  2. Each sub-packet is addressed separately to the correct physical DDR controller.
  3. Responses are re-assembled at the NMU and returned to the attached master.