- 1. Debug Tree
- This is the list of all of the debug elements in the design. For
the integrated memory interfaces, all four are displayed with status listed to
the right. A label of ‘DISABLED’ means that particular memory controller is not
used in the current configuration. Selecting a DDRMC will cause all windows to
update with the appropriate data.
The DDRMC_x is a label that notes the physical location of the memory controller on the device. DDRMC_1 is the memory controller on the far left, underneath the Processor. DDRMC_2 is the next on the right, and so on.
- 2. Core Properties
- This window contains three tabs: General, Properties, and
Configuration. The General tab displays basic status of the memory controller.
The Properties tab, shown in the following figure, lists out all of the internal registers for the memory controller.Figure 2. Memory Controller Core Properties: Properties Tab
A search is available by selecting the magnifying glass icon in the upper left. This is helpful to minimize the hundreds of properties when searching for specific information.
The Configuration tab, shown in the following figure, provides information on the configuration programmed into the memory controller such as data width, ranks, bytes, and memory frequency.Figure 3. Memory Controller Core Properties: Configuration Tab
- 3. Memory Controller Status
- This window provides the overall status of the memory controller. If there is an error in calibration, detailed information describing the issue will be displayed here, as well as the location of the failure such as which byte lanes or nibbles (if appropriate).
- 4. Calibration Stages
- This window lists all of the calibration states that are needed
to bring up the memory interface for a given configuration. Depending on the
memory type (DDR4 vs. LPDDR4) or the operating frequency of the memory, the
stages will vary.
In the event of a calibration error, the failing stage will be shown.
- 5. Margin Data
- This window, shown in the following figure, displays the margin data
obtained from calibration. There is margin data for both read and write modes.
For each mode there are also simple and complex patterns. This represents the
aggressiveness of the data pattern used. It is expected that complex data
patterns will result in a smaller window than the simple pattern due to more
bits transitioning and therefore generating more noise. There is also a
selection for the rising and falling edges of the DQS. Note: Calibration stages that generate Complex data margins are skipped at 2,133 Mbps and slower. Calibration stages that generate Simple data margins are skipped at 1,600 Mbps and slower. In these cases the corresponding margin data is not available.Figure 4. Memory Controller Margin Window: Table View
Margin data can also be viewed in a graph format (as shown in the following figure). It is easier to compare window margins for the various byte lanes this way. The dotted vertical line shows the size of the smallest window for comparison purposes. It does not signify a minimum margin for proper operation.
The graph view is helpful to identify any issues that may result from poor layout. If one nibble or byte lane is much smaller than the others, it is worthwhile to examine the layout of that lane for any routing rule violations.Figure 5. Memory Controller Margin Window: Chart View
Figure 1. Debug GUI