Memory Initialization - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The PHY issues commands to load the DDR4 Mode registers with values defined in the user IP settings. There are no debug registers associated with this calibration stage.