Memory Initialization and Calibration Sequence - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English
After deassertion of the system reset, the PHY performs the required internal calibration steps:
  1. The built-in self-check of the PHY (BISC) is run. BISC is used in the PHY to compute internal skews for use in voltage and temperature tracking after calibration is completed.
  2. After BISC is completed, calibration logic performs the required power-on initialization sequence for the memory.
  3. This is followed by several stages of timing calibration for the write and read datapaths.
  4. After calibration is completed the PHY calculates internal offsets to be used in voltage and temperature tracking.
  5. PHY indicates calibration is finished and the controller begins issuing commands to the memory.
Important: Calibration is only completed for MCs in NoC instances with at least one NMU. MCs without a path to memory through the NoC are not calibrated. For testing purposes, users can create a block design with CIPS driving the MC of interest.

The following figure shows the overall flow of memory initialization and the different stages of calibration. While the figure shows an interative loop to calibrate other ranks after all calibration stages have been completed for the first rank, in reality this iteration occurs on a stage-by-stage basis, after each stage is completed.

Figure 1. PHY Overall Initialization and Calibration Sequence