When more than one DDR controller is available on a device, you can choose between two mapping modes:
- Each DRAM controller is one contiguous address space which may be targeted independently.
- Two or four DRAM controllers may be interleaved to present a single unified address space.
Memory interleaving makes the participating memory controllers appear as one large pool of memory. The memory may still be spread across discontinuous physical regions like a single DDR controller, with a small region in 4 GB address space and a larger region somewhere higher in the address map. Memory traffic is balanced across the participating DDR controllers in hardware and software does not need to determine how to place data to effectively use more than one DDR controller.
The following figure shows an example of interleaved memory across two DDR controllers. The interleave granularity shown is 1K. The NoC manages interleaving at each NoC entry point (NMU). Interleaving is a property of a memory region. If a memory region is interleaved across two memory controllers, then half of the memory in the region goes to one controller and half goes to the other. The mapping is arranged in strided fashion such that alternate 1K regions go to different DDR controllers. If a burst transaction is sent to an NMU and crosses an interleave boundary (in this case 1K), the transaction is chopped at the interleave boundary. This ensures that a single transaction never crosses an interleave boundary.
- Explicit partitioning of the workload based on traffic type, function, or other considerations.
- Independent power mode switching and/or frequency changes.
- A unified address space.
- Automatic load balancing.
- 2x or 4x the bandwidth of a single 'pipe'.