Migration Options Tab - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

When migrating a design from one ACAP to another ACAP density with the same package, there are timing adjustments necessary for the Command/Address/Control (CAC) pins for the DDR interface. Even though the pinout remains the same, the package flight times for these pins will change and this must be accounted for to maintain the phase relationship to the CAC clock. For DDR4, this only applies for the CAC bus as they are not calibrated. For LPDDR4 the CAC bus is calibrated so this migration step is unnecessary and disabled in the GUI.

The device supports a skew difference of 0 to 200 pS.

The Migration Options tab is shown in the following figure for reference.

Figure 1. DDR Migration Options

The following tables show examples on the skew calculations that need to be entered in the Migration Options window while migrating the FPGA device. The procedure to retrieve the delay values for the source and target devices is available in the Migration chapter in the Versal ACAP PCB Design User Guide (UG863).

These delay values for all used pins are listed in columns 2 and 3 for the source and target devices, respectively. The difference in the delay of the target device from the source is mentioned in column 4. Note that the skew can be positive or negative. Because the GUI expects only the positive skew values, the column 4 values are adjusted in the column 5 such that the lowest skew difference becomes zero. The calculated values in column 5 are to be entered in Vivado as shown in the previous figure.

Table 1. Calculation for All Positive Skews
Port Name Source Device Delay (in ps) Target Device Delay (in ps) Skew (Target Source) Skew (Entered in GUI)
ADDR[0] 159 190 31 20
ADDR[1] 162 185 23 12
CK 154 165 11 0
CKE 160 182 22 11
CS 150 195 45 34

The lowest skew among all entries of column 4 in the previous table is +11 ps. Therefore, column 5 gets formed by subtracting this lowest skew value (+11 ps) from column 4.

Table 2. Calculation for All Negative Skews
Port Name Source Device Delay (in ps) Target Device Delay (in ps) Skew (Target Source) Skew (Entered in GUI)
ADDR[0] 189 150 -39 0
ADDR[1] 172 155 -17 22
CK 184 165 -19 20
CKE 170 162 -8 31
CS 180 175 -5 34

The lowest skew among all entries of column 4 in the previous table is -39 ps. Then, column 5 gets formed by subtracting this lowest skew value (-39 ps) from column 4.

Table 3. Calculation for Mix of Positive and Negative Skews
Port Name Source Device Delay (in ps) Target Device Delay (in ps) Skew (Target Source) Skew (Entered in GUI)
ADDR[0] 169 190 21 39
ADDR[1] 172 185 13 31
CK 154 165 11 29
CKE 170 152 -18 0
CS 180 175 -5 13

The lowest skew among all entries of column 4 in the previous table is -18 ps. Hence, column 5 gets formed by subtracting this lowest skew value (-18 ps) from column 4.