Monitoring ECC Status - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

Status registers to Find Correctable and Uncorrectable Errors

In HW manager, under DDRMC* ecc, the following status registers can be observed:
Note: Refresh the respective DDRMC to reflect the current status.
  • DDRMC_ISR_CE0_ECC0
  • DDRMC_ISR_CE0_ECC1
  • DDRMC_ISR_CE1_ECC0
  • DDRMC_ISR_CE1_ECC1
  • DDRMC_ISR_UC0_ECC0
  • DDRMC_ISR_UC0_ECC1
  • DDRMC_ISR_UC1_ECC0
  • DDRMC_ISR_UC1_ECC1
  • In the above status registers, the first 0 or 1 (CE* and UC*) indicates which half of the BLn burst contained an error, and the last 0 or 1 (ECC*) indicates the DDRMC channel number containine an error.
  • When one or more errors are injected, HW will set the reg_adec15.done bit to 0x1 under DDRMC_NOC* registers.
  • In persistent mode, errors will continue to be injected after the done bit is set.
  • In single mode (persistent=0x0) the done bit must be cleared to enable another single error injection.
  • During correctable error detection DRAM will be scrubbed.
  • During uncorrectable error detection SLVERR Read response will be returned to the host.