Multi-Thread Linear Read/Write - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

This example uses two read devices and two write devices, all operating concurrently, and each linearly accessing a different memory region. Similar to the previous example, it is beneficial for each device to open a page and access it linearly without page miss interruptions. To achieve this, ‘place’ each device in a separate bank, while keeping one bank group bit in the low order bits as before to avoid same-group penalty.

To achieve this, decide how to partition the memory between the four devices. For example, allocate 32 MB for each device. To ensure that each device is accessing a different bank, place the bank bits at the position corresponding to 32 MB boundary: 6R-2B-1BG-11R-7C-1BG-3C.

Table 1. Multi-Thread Linear Read/Write Address Mapping
Mapping Efficiency Mapping Type
6R-2B-1BG-11R-7C-1BG-3C 88% 32 MB multi-thread
16R-2B-1BG-7C-1BG-3C 40% Row-bank-column with bank group optimization
16R-2B-2BG-10C 29% Simple row-bank-column

This approach works well with up to eight devices because each device occupies two banks. With more than eight devices, some performance degradation is expected. Note that the 32MB choice is just an example. Another possibility is to place the three bank bits as most-significant bits, thus partitioning the entire DRAM space into eight equal regions.