NMU512 (PL) - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

The NMU512 is a full-featured NoC Master Unit, used to provide ingress to the vertical NoC (VNoC) channels from AXI master units in the Programmable Logic (PL) array. The NMU512 has a maximum AXI data width of 512 bits (64 bytes) and is configurable from 32 bits to 512 bits in AXI memory mapped mode, and 128 bits to 512 bits in AXI4-Stream mode. The NMU512 supports AXI4, Memory Mapped, and AXI4-Stream protocols.