NoC and Memory Controller Simulation - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-04-27
Version
1.0 English

NoC and Integrated Memory Controller simulation support is provided with behavioral models in either System Verilog (RTL in GUI) or SystemC (TLM in GUI). The simulation time with SystemC model is much faster but less accurate compared to the System Verilog model. While both the SystemC and System Verilog models can be used to verify functionality, the System Verilog model should be used for performance analysis. Performance includes both bandwidth and latency. Performance analysis using the System Verilog model is within +/- 5% of hardware. All supported memory densities can be simulated using the System Verilog model.

The System Verilog model is a behavioral model developed for performance analysis. The following features have minimal impact on performance and are hence not modeled:

  • Calibration algorithm
  • Memory initialization sequence – Model gets Mode Register values through parameters
  • ECC - Check Bit calculation is unsupported, however performance impact due to Check Bit calculation and Read Modify Write (RMW) is modeled
  • Initializing DRAM with data patterns
  • ECC Poisoning
  • Scrubbing – Performance impact is insignificant because it is a background activity
  • 2T timing – Performance impact is insignificant
  • DRAM Command/Address Parity – Retry resulting from Command/Address parity error not modeled
  • Write/Read DBI – Performance impact is modeled
  • Exclusive transactions – All transactions treated equally by the model
  • Programmable preamble and post amble for read and write
  • Self-Refresh, User Refresh
  • Page closed policy
  • CA Mirror