NoC and Memory Controller Simulation - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

NoC and Integrated Memory Controller simulation support is provided with behavioral models in either System Verilog (RTL in GUI) or SystemC (TLM in GUI). The simulation time with SystemC model is much faster but less accurate compared to the System Verilog model. While both the SystemC and System Verilog models can be used to verify functionality, the System Verilog model should be used for performance analysis. Performance includes both bandwidth and latency. Performance analysis using the System Verilog model is within +/- 5% of hardware. All supported memory densities can be simulated using the System Verilog model.

During simulation the Read Latency Estimate and Write Latency Estimate represent only the round-trip structural latency through a portion of the NoC in the AXI clock domain. These numbers do not include latency in the DRAM, memory controller, PCB routing, etc. The actual total latency will be greater than these numbers. These latencies are reported in AXI clock cycles. They are intended for relative comparison between different NoC implementations, not as a representation of the actual total latency.

The System Verilog model is a behavioral model developed for performance analysis. The following features have minimal impact on performance and are hence not modeled:

  • Calibration algorithm
  • ECC – Check Bit calculation is unsupported, however performance impact due to Check Bit calculation and Read Modify Write (RMW) is modeled
  • Initializing DRAM with data patterns
  • ECC Poisoning
  • Scrubbing – Performance impact is insignificant because it is a background activity
  • 2T timing – Performance impact is insignificant
  • DRAM Command/Address Parity – Retry resulting from Command/Address parity error not modeled
  • Write/Read DBI – Performance impact is modeled
  • Exclusive transactions – All transactions treated equally by the model
  • Programmable preamble and post amble for read and write
  • Self-Refresh, User Refresh
  • Page closed policy
  • CA Mirror
Note: HBM Controller simulation is currently supported with Vivado Simulator, ModelSim Simulator, Questa Advanced Simulator, Xcelium Parallel Simulator, and Synopsys Verilog Compiler Simulator (VCS). The HBM Controller simulation only supports SystemVerilog and not SystemC (tlm) simulation.
Note: When using Questa Advanced Simulator for designs with the HBM Controller, you need to set -inlineFactor=0 in the questa.elaborate.vopt.more_options. This can be done using the following command in the Tcl console:
set_property -name {questa.elaborate.vopt.more_options} -value {-inlineFactor=0} -objects [get_filesets sim_1]
Note: Simulation for clamshell configuration is currently not supported.