The NMU provides a register indicating the number of pending transactions. This is the number of original AXI transactions received on the AXI interface that have not yet completed. A transaction completes when the final valid/ready handshake of the last response occurs on the AXI interface.
There are separate pending transaction registers for read and write transactions. There is a separate register to indicate whether any read or write transactions are pending. This logic is used for cases where the NoC may need to be powered down or the NMU quiesced before reprogramming takes place.
The NMU also provides a control register to prevent any new transactions from entering the NMU. If there are any writes where the AW phase has been received then the W phases are allowed to complete before the interface blocks.