Overview of Performance Tuning - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

Following is an overview of performance tuning for the NoC and integrated DDRMC:

  1. Choose the traffic class for each NoC master.
    1. If the master has a cache, reads are low latency (LL) and writes are best effort.
    2. If the master has any hard or soft real-time requirements (for example video applications), the traffic class is isochronous (ISOC).
    3. Otherwise, choose best effort (BE). If unsure, this should be the default.
  2. Select bandwidth allocation for each flow. The bandwidth allocations determine what happens when all masters are trying to get service and there is contention.
    1. For LL traffic, the bandwidth allocation should be a small fraction of the available DDR bandwidth.
    2. For ISOC traffic, the bandwidth needed/generated by the master is typically known, and the allocation should match that bandwidth.
    3. For BE traffic, choose a minimum desired bandwidth.
  3. Configure masters to send the longest bursts possible. This will have the best DDR efficiency.
  4. Tune the DDR performance first before the NoC. Ensure row/bank/column mappings are optimized.
  5. If DDR performance is optimal but the overall NoC traffic specification is still not met:
    1. Examine shared routes through the NoC. Some masters might get less bandwidth than expected due to sub-optimal sharing of routes.
    2. A BE master might get less bandwidth than expected on reads due to finite read reorder buffer entries in the NMU.
      1. Moving the master closer to DDR can help.
      2. Increase the bandwidth allocation of the master. For BE traffic this might not always help. The NoC applies some traffic shaping to BE based on allocations, but the memory controller treats all BE traffic with equal priority.
      3. Other options are to make the master ISOC, or to rate limit other BE masters.
Note: For more information on tuning NoC performance, see Improving Performance Through the NoC in Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).