PHY BISC - 1.0 English

Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller 1.0 LogiCORE IP Product Guide (PG313)

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1.0 English

In this calibration stage, internal delays are measured to determine the number of fine taps required to equal a quarter clock memory period. This is referred to as a coarse tap.

Table 1. PHY BISC Calibration Register
Register Name Quantity Description
Fx_CALBISC_RL_DLY_QTR 1 Number of fine taps to equal ¼ memory clock period.