Parity - 1.0 English

Versal ACAP Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313)

Document ID
PG313
Release Date
2022-12-14
Version
1.0 English

AXI Parity is generated by the user in the AXI master or slave, and sent to the NMU or NSU at the AXI interface input. The NMU and NSU also generate AXI Parity at the AXI interface output.

Data and AxAddress parity covers the protocol domain (between the AXI interface and the conversion to NoC Packet Protocol (NPP)) for both the request and response directions, in both the NMU and NSU pipelines.

  • 1 bit per byte for Data
  • 1 bit per byte for AxAddress

Parity is checked in the NMU/NSU pipeline when an AXI field is consumed (used by logic). When an AXI field is modified by NMU/NSU logic, parity is regenerated.

For AXI requests with unaligned addresses, read/write data parity is checked from 16B-aligned addresses. For example, if the starting address of an AXI request is 0x4 and the AXI master/slave provides the wrong parity on byte 0x2, it is detected as a parity error. Write data parity is checked regardless of the AXI write strobe value.

For the NMU:
  • Address parity for read/write requests and data parity for write requests is generated by the user in the AXI master, and sent to the NMU at the AXI interface input.
  • Data parity for write requests is delivered along with the data and checked at the conversion from AXI protocol to NPP.
  • The AxAddress can be consumed and modified for address mapping/remapping and AXI chopping, so address parity is checked and regenerated in the NMU. Address map/remap regenerates seven parity bits [7:1], with parity bit 1 covering address nibble [15:12]. AXI chopping regenerates 1-bit parity [0] for the lower 12 address bits. Regenerated address parity is checked at the conversion from AXI protocol to NPP.
  • Data parity for read responses is generated as 1 bit per byte after the ECC check stage, when the data is converted from NPP to AXI protocol.
For the NSU:
  • Address parity for read/write requests and data parity for write requests is generated by the NSU after the ECC check.
  • Data parity for write requests is sent to the AXI slave as is, because byte-level data is not modified.
  • Address parity for read/write requests is also sent to the AXI slave as is for AXI4 protocol.
  • Data parity for read response is generated by the user in the Axi slave, sent to the NSU AXI interface input, and delivered along with data until it is checked at ECC generation stage.

Static fields in the NMU/NSU tracker entries are parity protected and checked when those fields are consumed. Tracker data buffers (NMU Read Reorder Buffer and NSU Read Tracker) are data parity protected.

The NPP packet (DST ID + LAST) field is also protected by 1-bit even parity. DST-ID parity is generated by the NMU/NSU and checked by the NPS. DST-ID parity is always generated regardless of AXI protocol (AXI4 request/response, AXI4-Stream).
  • The NMU generates DST-ID parity for read/write request NPP packets.
  • The NSU generates DST-ID parity for read/write response NPP packets.